Manuscript Oai279-A@1 · Oai279-A.tex · section · a1abc73f
A finite arithmetic table
Stage 6: the explicit circuit for the frozen input › A finite arithmetic table · lines 804–844
For , let be the complete sorted prime list. The following table supplies , the set of input bit positions where has a zero, and the set of output wires to be toggled.
| Binary | Gates | ||||
|---|---|---|---|---|---|
| 2 | 0010 | 13 | |||
| 3 | 0011 | 12 | |||
| 4 | 0100 | 14 | |||
| 5 | 0101 | 12 | |||
| 6 | 0110 | 13 | |||
| 7 | 0111 | 11 | |||
| 8 | 1000 | 15 | |||
| 9 | 1001 | 14 | |||
| 10 | 1010 | 13 | |||
| 11 | 1011 | 11 | |||
| 12 | 1100 | 14 | |||
| 13 | 1101 | 11 | |||
| 14 | 1110 | 12 | |||
| 15 | 1111 | 10 |
The output addresses follow (eq:output-address). For example, the first three entries begin at wires . Their low-bit encodings of have ones at .