Manuscript Oai279-A@1 · Oai279-A.tex · section · a1abc73f

A finite arithmetic table

Stage 6: the explicit circuit for the frozen input › A finite arithmetic table · lines 804–844

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For , let be the complete sorted prime list. The following table supplies , the set of input bit positions where has a zero, and the set of output wires to be toggled.

Binary Gates
2001013
3001112
4010014
5010112
6011013
7011111
8100015
9100114
10101013
11101111
12110014
13110111
14111012
15111110

The output addresses follow (eq:output-address). For example, the first three entries begin at wires . Their low-bit encodings of have ones at .

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