Manuscript Oai279-A@1 · Oai279-A.tex · section · a1abc73f

Frozen data and wire ledger

Stage 6: the explicit circuit for the frozen input › Frozen data and wire ledger · lines 774–803

Oai279-A@1#eq:frozen-input

Freeze

N_{0} = 12, ℓ_{0} = 4, n_{0} = 128.

The register allocation is:

Register	Wire addresses	Number of qubits
Input $I$	$0, 1, 2, 3$	$4$
Output $Y$	$4, \dots, 16387$	$12 8^{2} = 16384$
Scratch $u, v, f$	$16388, 16389, 16390$	$3$
Total	$0, \dots, 16390$	$16391$

Only the input is nonzero initially. Idle output wires count in the allocation; they are not free because the source uses a wide padded encoding.

We write $CCX (a, b; c)$ for the Toffoli gate with control wires $a, b$ and target $c$ , and $CX (a; c)$ for CNOT. The symbols $u, v, f$ denote the actual scratch addresses in the table, not additional unspecified registers.

Displayed formulas in this passage

Oai279-A@1#eq:frozen-input · line 777
$N_{0} = 12, ℓ_{0} = 4, n_{0} = 128.$