An elementary causal realization

A hardware implementation may give each local gate a hardware duration ${\delta }_{\mathrm{hw}}>0$. The certificate records

during the local stage. Along the positive-time apex worldline, $s_j=T_j/2$. Logical gate depth, hardware duration, and the model's slicing parameter are therefore explicitly different quantities.

The buffer is not a change in the cone's event. It is an added implementation latency around that event. An exact event code at model timestamp zero does not justify exposing its arbitrary compiler intermediate states as geometric configurations.