Proposition: Static-site register lower bound

Suppose an admissible realization uses $q=\left|X\right|$ sites and transmits payload influence from $0$ to $b$. Then

Also, its number $n$ of ticks satisfies

Proof. Influence requires $0\in N_0(\{b\})$, since otherwise the argument of Corollary cor:speed gives a replacement channel. Unwinding the ancestor recursion supplies a scheduled walk connecting $0$ to $b$, with one displacement of length at most $a_j$ per tick.

Form the undirected graph on $X$ containing every two-site block used by the circuit. The walk places $0$ and $b$ in the same connected component. A shortest graph path between them is simple, so it uses at most $q-1$ edges. Each edge has Euclidean length at most $a_j$. Consequently

This gives (eq:memory-lower). The scheduled walk similarly gives ${\Vert b\Vert }_2\le n{a}_j$.