Manuscript VII-E@1 · VII-E.tex · section · b713cf3c

Finite code and reversible implementation

One certified four-face slicing exchange › Finite code and reversible implementation · lines 2427–2487

VII-E@1#eq:clock, VII-E@1#eq:reports, VII-E@1#eq:event-code-map

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timing versus numerical reports. If an incoming length is , floor quantization at step reports zero throughout . A zero-report guard can therefore fire prematurely.

Fix an integer and store the exact parameter

in a signed -bit word. The event tests .

For report precision , store each length in an unsigned -bit word:

Every length is less than , so four integer bits suffice. Both central slots are retained; the inactive one is reported as zero. At the event both are zero.

The exact decoder reconstructs geometry from the fixed family, the mode, and exact , not from independent numerical edge labels. Reports must agree with eq:reports on its domain. The irrational arm reports can be precomputed exactly on the finite grid by comparisons of squared rational numbers.

chart data. The code includes identifiers for the charts in eq:charts, the collar chart, the prescribed transitions, the fixed exterior translation, and . All entries are rational. Only these listed data and products are needed; no finite closure under arbitrary Lorentz multiplication is asserted.

and history words. Fix a finite named matter interface of size . Let bits accommodate the union of pre- and post-event cell labels. Encode each location in an -bit word and provide a second -bit history word, initially zero. Invalid binary labels lie outside the decoder domain.

Let be the tuple of valid incoming location words. On the forward event domain, prescribe

where the permission word has bits. All fixed family identifiers are retained.

Displayed formulas in this passage

  • VII-E@1#eq:clock · line 2435

  • VII-E@1#eq:reports · line 2443

  • VII-E@1#eq:event-code-map · line 2476

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